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serial input 16-bit 4 maC20 ma, 0 maC20 ma dac ad420 rev. h information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?1999C2011 analog devices, inc. all rights reserved. features 4 maC20 ma, 0 maC20 ma or 0 maC24 ma current output 16-bit resolution and monotonicity 0.012% max integral nonlinearity 0.05% max offset (trimmable) 0.15% max total output error (trimmable) flexible serial digital interface (3.3 mbps) on-chip loop fault detection on-chip 5 v reference (25 ppm/c max) asynchronous clear function maximum power supply range of 32 v output loop compliance of 0 v to v cc ? 2.75 v 24-lead soic and pdip packages functional block diagram fault detect i out boost 40? 1.25k ? 4k? v out offset trim cap 1 cap 2 gnd v ll v cc ref out ref in data out clear latch clock data in range select 1 range select 2 ad420 reference data i/p register switched current sources and filtering clock 16-bit dac 00494-001 figure 1. general description the ad420 is a complete digital to current loop output converter, designed to meet the needs of the industrial control market. it provides a high precision, fully integrated, low cost single-chip solution for generating current loop signals in a compact 24-lead soic or pdip package. the output current range can be programmed to 4 ma to 20 ma, 0 ma to 20 ma or to an overrange function of 0 ma to 24 ma. the ad420 can alternatively provide a voltage output from a separate pin that can be configured to provide 0 v to 5 v, 0 v to 10 v, 5 v, or 10 v with the addition of a single external buffer amplifier. the 3.3 m baud serial input logic design minimizes the cost of galvanic isolation and allows for simple connection to commonly used microprocessors. it can be used in 3-wire or asynchronous mode and a serial-out pin is provided to allow daisy chaining of multiple dacs on the current loop side of the isolation barrier. the ad420 uses sigma-delta (-) dac technology to achieve 16-bit monotonicity at very low cost. full-scale settling to 0.1% occurs within 3 ms. the only external components that are required (in addition to normal transient protection circuitry) are two low cost capacitors which are used in the dac out- put filter. if the ad420 is used at extreme temperatures and supply voltages, an external output transistor can be used to minimize power dissipation on the chip via the boost pin. the fault detect pin signals when an open circuit occurs in the loop. the on-chip voltage reference can be used to supply a precision +5 v to external components in addition to the ad420 or, if the user desires temperature stability exceeding 25 ppm/c, an external precision reference such as the ad586 can be used as the reference. the ad420 is available in a 24-lead soic and pdip over the industrial temperature range of ?40c to +85c. product highlights 1. the ad420 is a single chip solution for generating 4 ma to 20 ma or 0 ma to 20 ma signals at the controller end of the current loop. 2. the ad420 is specified with a power supply range from 12 v to 32 v. output loop compliance is 0 v to v cc ? 2.75 v. 3. the flexible serial input can be used in 3-wire mode with spi? or microwire? microcontrollers, or in asynchronous mode, which minimizes the number of control signals required. 4. the serial data out pin can be used to daisy chain any number of ad420s together in 3-wire mode. 5. at power-up, the ad420 initializes its output to the low end of the selected range. 6. the ad420 has an asynchronous clear pin, which sends the output to the low end of the selected range (0 ma, 4 ma, or 0 v). 7. the ad420 boost pin accommodates an external transistor to off-load power dissipation from the chip. 8. the offset of 0.05% and total output error of 0.15% can be trimmed if desired, using two external potentiometers.
ad420 rev. h | page 2 of 16 table of contents features .............................................................................................. 1 ? functional block diagram .............................................................. 1 ? general description ......................................................................... 1 ? product highlights ........................................................................... 1 ? revision history ............................................................................... 2 ? specifications..................................................................................... 3 ? absolute maximum ratings............................................................ 5 ? esd caution.................................................................................. 5 ? pin configuration and function descriptions............................. 6 ? timing requirements ...................................................................... 7 ? three-wire interface ................................................................... 7 ? three-wire interface fast edges on digital input................... 7 ? asynchronous interface............................................................... 7 ? terminology ...................................................................................... 8 ? theory of operation ........................................................................ 9 ? applications information .............................................................. 10 ? current output ........................................................................... 10 ? driving inductive loads............................................................ 10 ? voltage-mode output................................................................ 10 ? optional span and zero trim .................................................. 10 ? three-wire interface ................................................................. 11 ? using multiple dacs with fault detect ................................. 11 ? asynchronous interface using optocouplers ........................ 11 ? microprocessor interface............................................................... 12 ? ad420-to-mc68hc11 (spi bus) interface........................... 12 ? ad420 to microwire interface ................................................. 12 ? external boost function ........................................................... 13 ? ad420 protection........................................................................... 14 ? transient voltage protection .................................................... 14 ? board layout and grounding ................................................. 14 ? power supplies and decoupling............................................... 14 ? outline dimensions ....................................................................... 15 ? ordering guide .......................................................................... 15 ? revision history 1/11rev. g to rev. h changes to figure 13...................................................................... 13 changes to ordering guide .......................................................... 15 11/09rev. f to rev. g updated format..................................................................universal changes to table 2............................................................................ 5 updated outline dimensions ....................................................... 15 changes to ordering guide .......................................................... 15 9/99rev. e to rev. f
ad420 rev. h | page 3 of 16 specifications t a = t min ? t max , v cc = +24 v, unless otherwise noted. table 1. ad420-32 version parameter min typ max units comments resolution 16 bits i out characteristics r l = 500 operating current ranges 4 20 ma 0 20 ma 0 24 ma current loop voltage compliance 0 v cc ? 2.75 v v settling time (to 0.1% of fs) 1 2.5 3 ms output impedance (current mode) 25 m accuracy 2 monotonicity 16 bits integral nonlinearity 0.002 0.012 % offset (0 ma or 4 ma) (t a = +25c) 0.05 % offset drift 20 50 ppm/ c total output error (20 ma or 24 ma) (t a = +25c) 0.15 % total output error drift 20 50 ppm/ c psrr 3 5 10 a/v v out characteristics fs output voltage range (pin 17) 0 5 v voltage reference ref out output voltage (t a = +25 c) 4.995 5.0 5.005 v drift 25 ppm/ c externally available current 5 ma short circuit current 7 ma ref in resistance 30 k v ll output voltage 4.5 v externally available current 5 ma short circuit current 20 ma digital inputs v ih (logic 1) 2.4 v v il (logic 0) 0.8 v i ih (v in = 5.0 v) 10 a i il (v in = 0 v) 10 a data input rate (3-wire mode) no minimum 3.3 mbps data input rate (asynchronous mode) no minimum 150 kbps digital outputs fault defec t v oh (10 k pull-up resistor to v ll ) 3.6 4.5 v v ol (10 k pull-up resistor to v ll ) 0.2 0.4 v v ol @ 2.5 ma 0.6 v data out v oh (i oh = ?0.8 ma) 3.6 4.3 v v ol (i ol = 1.6 ma) 0.3 0.4 v
ad420 rev. h | page 4 of 16 ad420-32 version parameter min typ max units comments power supply operating range v cc 12 32 v quiescent current 4.2 5.5 ma quiescent current (external v ll ) 3 ma temperature range specified performance ?40 +85 c 1 external capacitor selection must be as described in figure 6. 2 total output error includes offset and gain error. total output error and offset error are with respect to the full-scale outp ut and are measured with an ideal +5 v reference. if the internal reference is used, the reference errors must be added to the offset and total output errors. 3 psrr is measured by varying v cc from 12 v to its maximum 32 v.
ad420 rev. h | page 5 of 16 absolute maximum ratings table 2. parameter rating v cc to gnd 32 v i out to gnd v cc digital inputs to gnd ?0.5 v to +7 v digital output to gnd ?0.5 v to v ll + 0.3 v v ll and ref out: outputs safe for indefinite short to ground storage temperature ?65c to +150c lead temperature (soldering, 10 sec) +300c lead temperature, soldering reflow +260c thermal impedance: soic (r) package ja = 75c/w pdip (n) package ja = 50c/w stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 3. truth table inputs clear range select 2 range select 1 operation 0 x x normal operation 1 x x output at bottom of span x 0 0 0 vC5 v range x 0 1 4 maC20 ma range x 1 0 0 maC20 ma range x 1 1 0 maC24 ma range esd caution
ad420 rev. h | page 6 of 16 pin configuration and fu nction descriptions 00494-002 nc 1 v ll 2 fault detect 3 range select 2 4 nc 24 v cc 23 nc 22 cap 2 21 range select 1 5 cap 1 20 clear 6 boost 19 latch 7 i out 18 clock 8 v out 17 data in 9 offset trim 16 data out 10 ref in 15 gnd 11 ref out 14 nc 12 nc 13 nc = no connect ad420 top view (not to scale) figure 2. pin configuration table 4. pin function descriptions pin no. mnemonic function 1, 12, 13, 24 nc no connection. no internal connections inside device. 2 v ll auxiliary buffered +4.5 v digital logic voltage. this pin is the internal supply voltage for the digital circuitry and can be used as a termination for pull-up resistors. an external +5 v power supply can be connected to v ll . it will override this buffered voltage, thus reducing the internal power dissipation. the v ll pin should be decoupled to gnd with a 0.1 f capacitor. see the power supplies and decoupling section. 3 fault detect fault detect, connected to a pull-up resistor, is asserted low when the output current does not match the dacs programmed value, for example, in case the current loop is broken. 4 range select 2 selects the converters output operating range. one output voltage range and three 5 range select 1 output current ranges are available. 6 clear valid v ih unconditionally forces the output to go to the minimum of its programmed range. after clear is removed the dac output will remain at this value. the data in the input register is unaffected. 7 latch in the 3-wire interface mode a rising edge parallel lo ads the serial input register data into the dac. to use the asynchronous mode connect latch through a current limiting resistor to v cc . 8 clock data clock input. the clock period is equal to the inp ut data bit rate in the 3-wire interface mode and is 16 times the bit rate in asynchronous mode. 9 data in serial data input. 10 data out serial data output. in the 3-wire interface mode, th is output can be used for daisy-chaining multiple ad420s. in the asynchronous mode a positive pulse will indicate a framing error after the stop-bit is received. 11 gnd ground (common). 14 ref out +5 v reference output. 15 ref in reference input. 16 offset trim offset adjust. 17 v out voltage output. 18 i out current output. 19 boost connect to an external transistor to reduce th e power dissipated in the ad420 output transistor, if desired. 20 cap 1 these pins are used for internal filtering. connect capacitors between each of these 21 cap 2 pins and v cc . refer to the description of current output operation. 22 nc no connection. do not connect anything to this pin. 23 v cc power supply input. the v cc pin should always be decoupled to gnd with a 0.1 f capacitor. see the power supplies and decoupling section.
ad420 rev. h | page 7 of 16 timing requirements clock data in clock data in (internally generated latch) expanded time view below clock counter starts here confirm start bit sample bit 15 start bit data bit 15 bit 14 expanded time view below clock data in 01 012 8 16 24 001 start bit stop bit next start bit bit13 to bit1 bit15 bit14 bit0 t adw t ads t adh t ach t acl t ack 00494-004 t a = ?40c to +85c, v cc = +12 v to +32 v. three-wire interface clock data in latch data out clock data in latch data out word ?n? word ?n + 1? word ?n ? 1? word ?n? 1011001 1 1 00 1 1 1110 0 0 0 11 01 (msb) b15 (lsb) b15 b14 b13 b12 b14 b13 b12 b11 b10 b14 b15 b13 b12 b8 b7 b3 b2 b1 b0 b9 b5 b4 b6 t ck t cl t ch t dw t ld t ll t lh t sd t ds t dh 00494-003 figure 4. timing diagram for asynchronous interface figure 3. timing diagram for 3-wire interface tale 6. timing specifications for asynchronous interface parameter label limit units asynchronous clock period t ack 400 ns min asynchronous clock low time t acl 50 ns min asynchronous clock high time t ach 150 ns min data stable width (critical clock edge) t adw 300 ns min data setup time (critical clock edge) t ads 60 ns min data hold time (critical clock edge) t adh 20 ns min clear pulse width t clr 50 ns min table 5. timing specification for 3-wire interface parameter label limit units data clock period t ck 300 ns min data clock low time t cl 80 ns min data clock high time t ch 80 ns min data stable width t dw 125 ns min data setup time t ds 40 ns min data hold time t dh 5 ns min latch delay time t ld 80 ns min latch low time t ll 80 ns min latch high time t lh 80 ns min serial output delay time t sd 225 ns max clear pulse width t clr 50 ns min asynchronous interface note that in the timing diagram for asynchronous mode oper- ation each data word is framed by a start (0) bit and a stop (1) bit. the data timing is with respect to the rising edge of the clock at the center of each bit cell. bit cells are 16 clocks long, and the first cell (the start bit) begins at the first clock following the leading (falling) edge of the start bit. thus, the msb (d15) is sampled 24 clock cycles after the beginning of the start bit, d14 is sampled at clock number 40, and so on. during any dead time before writing the next word the data in pin must remain at logic 1. three-wire interface fast edges on digital input with a fast rising edge (<10 ns) on one of the serial inputs (clock, data in, latch) while another input is logic high, the part may be triggered into a test mode and the contents of the data register may become corrupted, which may result in the output being loaded with an incorrect value. if fast edges are expected on the digital input lines, it is recommended that the latch line remain at logic 0 during serial loading of the dac. similarly, the clock line should remain low during updates of the dac via the latch pin. alternatively, the addition of small value capacitors on the digital lines will slow down the edge. the dac output updates when the stop bit is received. in the case of a framing error (the stop bit sampled as a 0) the ad420 will output a pulse at the data out pin one clock period wide during the clock period subsequent to sampling the stop bit. the dac output will not update if a framing error is detected.
ad420 rev. h | page 8 of 16 terminology resolution for 16-bit resolution, 1 lsb = 0.0015% of the fsr. in the 4 maC20 ma range 1 lsb = 244 na. integral nonlinearity analog devices defines integral nonlinearity as the maximum deviation of the actual, adjusted dac output from the ideal analog output (a straight line drawn from 0 to fs C 1 lsb) for any bit combination. this is also referred to as relative accuracy. differential nonlinearity differential nonlinearity is the measure of the change in the analog output, normalized to full scale, associated with an lsb change in the digital input code. monotonic behavior requires that the differential linearity error be greater than C1 lsb over the temperature range of interest. monotonicity a dac is monotonic if the output either increases or remains constant for increasing digital inputs with the result that the output will always be a single-valued function of the input. gain error gain error is a measure of the output error between an ideal dac and the actual device output with all 1s loaded after offset error has been adjusted out. offset error offset error is the deviation of the output current from its ideal value expressed as a percentage of the fullscale output with all 0s loaded in the dac. drift drift is the change in a parameter (such as gain and offset) over a specified temperature range. the drift temperature coefficient, specified in ppm/c, is calculated by measuring the parameter at t min , 25c, and t max and dividing the change in the parameter by the corresponding temperature change. current loop voltage compliance the voltage compliance is the maximum voltage at the i out pin for which the output current will be equal to the programmed value.
ad420 rev. h | page 9 of 16 theory of operation the ad420 uses a sigma-delta (-) architecture to carry out the digital-to-analog conversion. this architecture is particularly well suited for the relatively low bandwidth requirements of the industrial control environment because of its inherent monotonicity at high resolution. in the ad420 a second order modulator is used to keep com- plexity and die size to a minimum. the single bit stream from the modulator controls a switched current source that is then filtered by two, continuous time resistor-capacitor sections. the capacitors are the only external components that have to be added for standard current-out operation. the filtered current is amplified and mirrored to the supply rail so that the application simply sees a 4 maC20 ma, 0 maC20 ma, or 0 maC24 ma current source output with respect to ground. the ad420 is manufactured on a bicmos process that is well suited to implementing low voltage digital logic with high performance and high voltage analog circuitry. the ad420 can also provide a voltage output instead of a current loop output if desired. the addition of a single external amplifier allows the user to obtain 0 vC5 v, 0 vC10 v, 5 v, or 10 v. the ad420 has a loop fault detection circuit that warns if the voltage at i out attempts to rise above the compliance range, due to an open-loop circuit or insufficient power supply voltage. the fault detect is an active low open drain signal so that one can connect several ad420s together to one pull-up resistor for global error detection. the pull-up resistor can be tied to the v ll pin, or an external +5 v logic supply. the i out current is controlled by a pmos transistor and an internal amplifier as shown in the functional block diagram. the internal circuitry that develops the fault output avoids using a comparator with window limits since this would require an actual output error before the fault detect output becomes active. instead, the signal is generated when the internal amplifier in the output stage of the ad420 has less than approximately one volt remaining of drive capability (when the gate of the output pmos transistor nearly reaches ground). thus the fault detect output activates slightly before the compliance limit is reached. since the comparison is made within the feedback loop of the output amplifier, the output accuracy is maintained by its open-loop gain, and no output error occurs before the fault detect output becomes active. the 3-wire digital interface, comprising data in, clock, and latch, interfaces to all commonly used serial micropro- cessors without the addition of any external glue logic. data is loaded into an input register under control of clock and is loaded to the dac when latch is strobed. if a user wants to minimize the number of galvanic isolators in an intrinsically safe application, the ad420 can be configured to run in asynchronous mode. this mode is selected by connecting the latch pin to v cc through a current limiting resistor. the data must then be combined with a start and stop bit to frame the information and trigger the internal latch signal. fault detect i out boost 40? 1.25k ? 4k? v out offset trim cap 1 cap 2 gnd v ll v cc ref out ref in data out clear latch clock data in range select 1 range select 2 ad420 reference data i/p register switched current sources and filtering clock 16-bit dac 00494-005 2 19 23 18 17 3 21 11 20 16 14 15 10 6 7 8 9 5 4 figure 5. functional block diagram
ad420 rev. h | page 10 of 16 applications information current output the ad420 can provide 4 maC20 ma, 0 maC20 ma, or 0 maC 24 ma output without any active external components. filter capacitors c1 and c2 can be any type of low cost ceramic capacitors. to meet the specified full-scale settling time of 3 ms, low dielectric absorption capacitors (npo) are required. suitable values are c1 = 0.01 f and c2 = 0.01 f. 00494-006 5 2 20 14 15 11 21 23 4 6 18 7 8 9 i out (4ma to 20ma) r load v cc v ll ad420 gnd 0.1f 0.1f ref in ref out c1 c2 data in clock latch clear range select 2 range select 1 figure 6. standard configuration driving inductive loads when driving inductive or poorly defined loads ,connect a 0.01 f capacitor between i out (pin 18) and gnd (pin 11). this ensures stability of the ad420 with loads beyond 50 mh. there is no maximum capacitance limit. the capacitive component of the load may cause slower settling, though this may be masked by the settling time of the ad420. a programmed change in the current may cause a back emf voltage on the output that may exceed the compliance of the ad420. to prevent this voltage from exceeding the supply rails connect protective diodes between i out and each of v cc and gnd. voltage-mode output since the ad420 is a single supply device, it is necessary to add an external buffer amplifier to the v out pin to obtain a selection of bipolar output voltage ranges as shown in figure 7 . 00494-007 5 2 20 14 15 11 21 23 4 6 17 7 8 9 v out v out r2 r3 r1 v cc v ll ad420 gnd 0.1f 0.1f ref in ref out c1 c2 data in clock latch clear range select 2 range select 1 figure 7. tale 7. buffer amplifier configuration r1 r2 r3 v out open open 0 0 v ? 5 v open r r r open r 5 v r 2r 2r 10 v suitable r = 5 k. optional span and zero trim for users who would like lower than the specified values of offset and gain error, figure 8 shows a simple way to trim these parameters. care should be taken to select low drift resistors because they affect the temperature drift performance of the dac. the adjustment algorithm is iterative. the procedure for trimming the ad420 in the 4 maC20 ma mode can be accomplished as follows: 1. offset adjust. load all zeros. adjust rzero for 4.00000 ma of output current. 2. gain adjust. load all ones. adjust rspan for 19.99976 ma (fs ? 1 lsb) of output current. return to step i and iterate until convergence is obtained. 00494-008 5 2 20 14 15 16 11 21 23 4 6 18 19 7 8 9 i out (4ma to 20ma) r load 5k? rspan2 500 ? rspan 10k ? rzero boost v cc ad420 gnd ref out c1 c2 data in clock latch clear range select 2 range select 1 v ll 0.1f 0.1f figure 8. offset and gain adjust variation of rzero between ref out (5 v) and gnd leads to an offset adjust range from ?1.5 ma to 6 ma, (1.5 ma/v centered at 1 v). the 5 k rspan2 resistor is connected in parallel with the internal 40 w sense resistor, which leads to a gain increase of +0.8%. as rspan is changed to 500 , the voltage on ref in is attenuated by the combination of rspan and the 30 k ref in input resistance. when added together with rspan2 this results in an adjustment range of ?0.8% to +0.8%.
ad420 rev. h | page 11 of 16 three-wire interface figure 9 shows the ad420 connected in the 3-wire interface mode. the ad420 data input block contains a serial input shift register and a parallel latch. the contents of the shift register are controlled by the data in signal and the rising edges of the clock. upon request of the latch pin the dac and internal latch are updated from the shift register parallel outputs. the clock should remain inactive while the dac is updated. refer to the timing requirements for 3-wire interface. 00494-009 fault detect fault detect data in clock gnd latch data in clock latch v cc r load v cc i out data out ad420 dac1 fault detect data in clock gnd latch v cc v ll r load v cc i out data out ad420 dac2 10k ? figure 9. three-wire interface using mu ltiple dacs with joint fault detect using multiple dacs with fault detect the 3-wire interface mode can utilize the serial data out for easy interface to multiple dacs. to program the two ad420s in figure 9 , 32 data bits are required. the first 16 bits are clocked into the input shift register of dac1. the next 16 bits transmitted pass the first 16 bits from the data out pin of dac1 to the input register of dac2. the input shift registers of the two dacs operate as a single 32-bit shift register, with the leading 16 bits representing information for dac2 and the trailing 16 bits serving for dac1. each dac is then updated upon request of the latch pin. the daisy-chain can be extended to as many dacs as required. asynchronous interface using optocouplers the ad420 connected in asynchronous interface mode with optocouplers is shown in figure 10 . asynchronous operation minimizes the number of control signals required for isolation of the digital system from the control loop. the resistor connected between the latch pin and v cc is required to activate this mode. for operation with v cc below 18 v use a 50 k pull-up resistor; from 18 v to 32 v, use 100 k. asynchronous mode requires that the clock run at 16 times the data bit rate, therefore, to operate at the maximum input data rate of 150 kbps, an input clock of 2.4 mhz is required. the actual data rate achieved may be limited by the type of optocouplers chosen. the number of control signals can be further reduced by creating the appropriate clock signal on the current loop side of the isolation barrier. if optocouplers with relatively slow rise and fall times are used, schmitt triggers may be required on the digital inputs to prevent erroneous data being presented to the dac. 00494-010 8 2 7 23 9 11 v cc +24 v +5v v ll latch 100k ? ad420 clock data in isolation galvanic barrier clock data gnd figure 10. asynchronous interface using optocouplers
ad420 rev. h | page 12 of 16 microprocessor interface ad420-to-mc68hc11 (spi bus) interface the ad420 interface to the motorola serial peripheral interface (spi) is shown in figure 11 . the mosi, sck, and ss pins of the hc11 are respectively connected to the data in, clock, and latch pins of the ad420. the majority of the interfacing issues are done in the software initialization. a typical routine, such as the one shown below, begins by initializing the state of the various spi data and control registers. init ldaa #$2f ; ss = 1; sck = 0; mosi = 1 staa portd ;send to spi outputs ldaa #$38 ; ss , sck, mosi = outputs staa ddrd ;send data direction info ldaa #$50 ;dabl intrpts, spi is master & on staa spcr ;cpol = 0, cpha = 0, 1mhz baudrate nextpt ldaa msby ;load accum w/upper 8 bits bsr sendat ;jump to dac output routine jmp nextpt ;infinite loop sendat ldy #$1000 ;point at on-chip registers bclr $08,y,$20 ;drive ss (latch) low staa spdr ;send ms-byte to spi data reg wait1 ldaa spsr ;check status of spie bpl wait1 ;poll for end of x- mission ldaa lsby ;get low 8 bits from memory staa spdr ;send ls-byte to spi data reg wait2 ldaa spsr ;check status of spie bpl wait2; ;poll for end of x- mission bset $08,y,$20 ;drive ss high to latch data rts the spi data port is configured to process data in 8-bit bytes. the most significant data byte (msby) is retrieved from memory and processed by the sendat routine. the ss pin is driven low by indexing into the portd data register and clear bit 5. the msby is then sent to the spi data register where it is automatically transferred to the ad420 internal shift resister. the hc11 generates the requisite eight clock pulses with data valid on the rising edges. after the msby is transmitted, the least significant byte (lsby) is loaded from memory and transmitted in a similar fashion. to complete the transfer, the latch pin is driven high when loading the complete 16-bit word into the ad420. 00494-011 data in clock latch mosi sck ss 68hc11 ad420 figure 11. ad420-to-68hc11 (spi) interface ad420 to microwire interface the flexible serial interface of the ad420 is also compatible with the national semiconductor microwire interface. the microwire interface is used in microcontrollers such as the cop400 and cop800 series of processors. a generic interface to use the microwire interface is shown in figure 12 . the g1, sk, and so pins of the microwire interface are respectively connected to the latch, clock, and data in pins of the ad420. 00494-012 data in clock latch so sk g1 microwire ad420 figure 12. ad420-to-microwire interface
ad420 rev. h | page 13 of 16 external boost function the external boost transistor reduces the power dissipated in the ad420 by reducing the current flowing in the on-chip output transistor (dividing it by the current gain of the external circuit). a discrete npn transistor with a breakdown voltage, bv ceo , greater than 32 v can be used as shown in figure 13 . 00494-013 ad420 mjd31c or 2n3053 19 boost i out 0.022f 1k? r load 18 figure 13. external boost configuration the external boost capability has been developed for those users who may wish to use the ad420, in the soic package, at the extremes of the supply voltage, load current, and temperature range. the pdip package (because of its lower thermal resistance) will operate safely over the entire specified voltage, temperature, and load current ranges without the boost transistor. the plot in figure 14 shows the safe operating region for both package types. the boost transistor can also be used to reduce the amount of temperature induced drift in the part. this will minimize the temperature induced drift of the on-chip voltage reference, which improves drift and linearity. 00494-014 28v 20v 12v 4v ?60 ?40 ?20 0 20 40 60 80 100 temperature (c) 25v ad420 or ad420-32 32v v cc when using soic packaged devices, an external boost transistor is required for operation in this area. figure 14. safe operating region
ad420 rev. h | page 14 of 16 ad420 protection transient voltage protection the ad420 contains esd protection diodes, which prevent damage from normal handling. the industrial control envir- onment can, however, subject i/o circuits to much higher transients. to protect the ad420 from excessively high voltage transients, such as those specified in iec 801, external power diodes and a surge current limiting resistor may be required, as shown in figure 15 . the constraint on the resistor is that during normal operation the output voltage level at i out must remain within its voltage compliance limit ( i out (rp + r load ) v cc ? 2.75 v ) and the two protection diodes and resistor must have appropriate power ratings. 00494-015 ad420 i out v cc v cc r load r p gnd figure 15. output transient voltage protection board layout and grounding the ad420 ground pin, designated gnd, is the high quality ground reference point for the device. any external loads on the ref out and v out pins of the ad420 should be returned to this reference point. analog and digital ground currents should not share a common path. each sign al should have an appropriate analog or digital signal return routed close to it. using this approach, signal loops enclose a small area, minimizing the inductive coupling of noise. wide pc tracks, large gauge wire, and ground planes are highly recommended to provide low impedance signal paths. power supplies and decoupling the ad420 supply pins, v cc (pin 23) and v ll (pin 2), should be decoupled to gnd with 0.1 f capacitors to eliminate high frequency noise that may otherwise get coupled into the analog system. high frequency ceramic capacitors are recommended. the decoupling capacitors should be located in close proximity to the pins and the ground line to have maximum effect. further reductions in noise, and improvements in performance, may be achieved by using a larger value capacitor on the v ll pin.
ad420 rev. h | page 15 of 16 outline dimensions controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. corner leads may be configured as whole or half leads. compliant to jedec standards ms-001 071006-a 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.150 (3.81) 0.130 (3.30) 0.115 (2.92) 0.070 (1.78) 0.060 (1.52) 0.045 (1.14) 24 1 12 13 0.100 (2.54) bsc 1.280 (32.51) 1.250 (31.75) 1.230 (31.24) 0.210 (5.33) max seating plane 0.015 (0.38) min 0.005 (0.13) min 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.060 (1.52) max 0.430 (10.92) max 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.015 (0.38) gauge plane 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) figure 16. 24-lead plastic dual in-line package [pdip] narrow body (n-24-1) dimensions shown in inches and (millimeters) compliant to jedec standards ms-013-ad controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. 15.60 (0.6142) 15.20 (0.5984) 0.30 (0.0118) 0.10 (0.0039) 2.65 (0.1043) 2.35 (0.0925) 10.65 (0.4193) 10.00 (0.3937) 7.60 (0.2992) 7.40 (0.2913) 0 . 7 5 ( 0 . 0 2 9 5 ) 0 . 2 5 ( 0 . 0 0 9 8 ) 45 1.27 (0.0500) 0.40 (0.0157) coplanarity 0.10 0.33 (0.0130) 0.20 (0.0079) 0.51 (0.0201) 0.31 (0.0122) seating plane 8 0 24 13 12 1 1.27 (0.0500) bsc 06-07-2006-a figure 17. 24-lead standard small outline [soic_w] wide body (rw-24) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range max operating voltage package description package option ad420an-32 ?40c to +85 c 32 v 24-lead pdip n-24-1 ad420anz-32 ?40c to +85 c 32 v 24-lead pdip n-24-1 ad420ar-32 ?40c to +85 c 32 v 24-lead soic_w rw-24 AD420AR-32-REEL ?40c to +85 c 32 v 24-lead soic_w rw-24 ad420arz-32 ?40c to +85 c 32 v 24-lead soic_w rw-24 ad420arz-32-reel ?40c to +85 c 32 v 24-lead soic_w rw-24 1 z = rohs compliant part.
ad420 rev. h | page 16 of 16 notes ?1999C2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d00494-0-1/11(h)

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